Complementary metal-oxide-semiconductor (CMOS) technology has served as the structural backbone of the semiconductor industry for more than five decades, evolving from micrometer-scale planar transistors to sub-2-nanometer three-dimensional architectures. This review synthesizes the trajectory of CMOS scaling across all major technology nodes, beginning with the empirical foundations laid by Moore's Law and Dennard's constant-field scaling theory, and progressing through the strain-engineered, high-k/metal-gate planar transistors of the 90-32 nm era, the tri-gate FinFET architectures that dominated the 22-7 nm nodes, and the gate-all-around (GAA) nanosheet and nanowire transistors now enabling the 5-2 nm regime. Particular attention is given to the enabling role of extreme ultraviolet (EUV) lithography, the persistent challenge of leakage power following the breakdown of Dennard scaling, and emerging post-CMOS strategies including complementary field-effect transistors (CFETs), monolithic 3D integration, and two-dimensional (2D) channel materials such as transition metal dichalcogenides. By critically examining device physics, process innovations, and the economic constraints that shape roadmap decisions, this review identifies electrostatic control, contact resistivity, and heterogeneous material integration as the dominant bottlenecks for future scaling and outlines the architectural pathways most likely to sustain transistor density growth beyond the 1 nm node.
CMOS scaling; Moore's Law; Dennard scaling; FinFET; gate-all-around (GAA); nanosheet transistor; EUV lithography; high-k metal gate; complementary FET (CFET); 2D semiconductors.
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